The term “programmable gate array” or “PGA” as used in the instant application is intended to cover all integrated circuits which incorporate a digital design, like logic arrays, application specific integrated circuits (ASICs), custom designs and the like. In order to program a digital design into a PGA, the design is first described through an English like textual programming language known as hardware design source language or HDL. There are many different HDLs on the market, like Verilog and VHDL, for example. Once the design is written in HDL and before the PGA is programmed (i.e. pre-implementation), a behavioral HDL design file or program is created and tested by computer simulation to verify that the design functions as intended. To test the HDL design, a HDL test bench file or program (or test fixture) is written which, when executed, applies stimulus to the design, then verifies the expected response via computer pre-implementation simulation. Once the HDL design has been verified at the pre-implementation stage, it is then synthesized to create a HDL net list file which is post-implementation computer simulated to verify that the timing of the implemented design meets the user's goals, and that the HDL design was implemented correctly. If the test bench file does not simulate with the post-synthesis net list file, the test bench file is updated by hand re-coding until it can simulate with the synthesized net list file.
Currently, most hardware designers develop test bench files for the behavioral HDL designs by hand. They computer simulate the HDL design with the corresponding test bench file or files to make sure the behavioral HDL design functions as intended. Next, the HDL design is implemented via synthesis, and the resulting post-implementation net list file is exported which includes a functional design description and timing information. The user then attempts to computer simulate this net list file with the original behavioral test bench file. In many instances there is no problem.
However, in a number of circumstances, the net list file does not match with the behavioral HDL design and thus, can not be computer simulated with the original test bench file without suitable modification. The net list file may not simulate because the original HDL design is changed during synthesis as a result of the transformations that occur, thus, making the resulting net list file incompatible with the original test bench file. Such transformations include data type remapping (for example, in VHDL, integers and signed/unsigned vectors are remapped to std_logic_vector), signal additions (such as global reset lines), signal elimination (such as inputs optimized out) and the like. Therefore, in these instances, the designer will modify the behavioral test bench file to simulate with the implemented net list. The modifications may include updating all assignments, ports, assertions, and related code—and can involve a great deal of labor-intensive hand re-coding depending on the complexity of the design, the data types used, and the implementation results. Additionally, these modifications need to be made for all test bench files associated with the HDL design file (large designs may have dozens, or even hundreds of test bench files), and such test bench files need to be continually updated as design changes are made to the original HDL design in order to computer simulate the modified design at the post-implementation stage.
The present invention intends to overcome the aforementioned drawbacks of the post-implementation methods of computer simulation of a HDL design by reducing substantially the labor-intensive re-coding activity involved in updating the original test bench files of a HDL design file.